SystemVerilog UVM Verification Contract

Canada citizen only. This is a remote contract role, and candidates must complete a background check and employment history verification.

I have an RTL block, chip or SoC described in SystemVerilog that now needs full functional verification. All verification work must follow UVM, from environment architecture through coverage closure, so that results can be maintained and extended by the in-house team once the contract ends.

Scope of work
• Build or adapt a complete UVM environment around the supplied DUT, including sequencer, driver, monitor, scoreboard and any passive agents needed for interfaces already defined in the spec.
• Develop constrained-random and directed sequences that exercise every item in the functional specification, aiming for 100 % functional and line coverage.
• Automate regressions and provide repeatable run scripts (Make, Python or similar) that can execute on our existing simulation farm.
• Deliver clear documentation: environment overview, user guide, test plan cross-referenced to coverage points and the final coverage report generated by the simulator.

Acceptance criteria
1. All tests run clean with no unexpected errors or warnings on VCS (our target simulator).
2. Functional coverage and code coverage each reach the agreed thresholds in the signed-off test plan.
3. The environment compiles with UVM-1.2 packages and passes the UVM compliance checker.
4. Scripts allow a one-command regression run that reproduces the coverage numbers supplied in the final report.

Source code will be exchanged through our private Git repository; commits must follow the existing branching strategy and include meaningful messages. I am available daily for questions and sync-ups and will review progress against milestones we define together at project kick-off.