Independent PCB Pre-Fabrication Peer Review

## Project title

**Senior Electronics / PCB Engineer Needed for Independent Pre-Fabrication Peer Review — KiCad, ESP32-S3, PoE, Ethernet, NFC, Precision ADC**

I am looking for an experienced **senior electronics/PCB design engineer** to carry out a genuinely independent pre-fabrication review of a completed 4-layer PCB before I commit to manufacturing the first five assembled boards.

This is **not a PCB design-from-scratch project**, and I am not looking for somebody simply to run DRC or tell me that KiCad reports no errors.

The design has already been through extensive development and currently reports:

* Schematic ERC: 0 errors / 0 warnings
* PCB DRC: 0 errors / 0 unconnected items
* Complete native KiCad project
* Final BOM and CPL
* Gerber and drill manufacturing outputs

What I want now is a **fresh pair of experienced eyes with no involvement in the original design** to independently determine whether there is anything that could cause the first five assembled boards to fail, behave incorrectly, be unreliable, be difficult to bring up/test, or be manufactured incorrectly.

### Main hardware on the board

The design includes:

* ESP32-S3-WROOM-1-N16R8 MCU / Wi-Fi / Bluetooth
* Native USB-C programming/debug
* ADS1232 24-bit precision bridge/load-cell ADC
* ST25R200 13.56 MHz NFC/HF reader with external antenna and VNA-tunable matching network
* W5500 10/100 Ethernet controller/PHY
* Integrated Ethernet magnetics / PoE RJ45
* IEEE 802.3af isolated PoE module
* TPS2121 USB/PoE power-source mux
* AP63203Q 3.3 V synchronous buck regulator
* Precision reference and power-priority circuitry
* ESD/surge protection
* Mixed analogue, digital, RF, Ethernet and power circuitry
* Mixed SMT and through-hole assembly

### What I need reviewed

I want a proper **schematic + PCB layout + BOM + footprint + manufacturing-data review**.

Please independently check areas including:

* every major IC pinout against current manufacturer documentation;
* mandatory support components and reference circuits;
* power architecture and rail sequencing;
* USB and PoE power interaction;
* isolated PoE implementation and isolation boundaries;
* TPS2121 priority/current-limit network;
* regulator component selection, switching loops and thermal layout;
* ESP32-S3 boot/reset/strapping and module antenna clearance;
* native USB D+/D- implementation and protection;
* W5500 power, reset, crystal, EXRES and SPI implementation;
* Ethernet MDI routing, terminations, magnetics and RJ45 pin mapping;
* controlled-impedance / return-path considerations;
* ADS1232 ratiometric bridge/load-cell arrangement;
* analogue supply/reference design, filtering, grounding and likely noise/drift risks;
* ST25R200 power, crystal, reset, SPI, RF input/output network and layout;
* NFC matching-network topology and suitability for later physical VNA tuning;
* critical/custom footprints against manufacturer mechanical drawings;
* connector pinouts and drill dimensions;
* protection parts, TVS devices, ferrites, fuses and polarity-sensitive components;
* BOM MPN/value/package compatibility;
* first-article DNP and variant states;
* Gerber/drill/CPL/BOM consistency;
* assembly and DFM concerns;
* first-article testability.

There is one deliberately documented local PCB clearance exception in a very tight NFC IC escape area. I want this independently assessed rather than simply accepted because the current DRC rule permits it.

### Important custom / critical parts

Particular attention should be given to the independently-created or tightly constrained footprints for:

* Taoglas TMJ6049BGNL MagJack
* Silvertel AG9905MT Gull Wing SMT PoE module
* TDK CKG57NX7R1E107M500JJ capacitor
* ST25R200 QFN
* TPS2121 VQFN-HR

Some components are intentionally locked to exact manufacturer part numbers for these first articles.

### What I do NOT want

I am not asking for:

* firmware development or review;
* cloud/software work;
* a complete PCB redesign;
* cosmetic layout changes;
* production cost optimisation;
* final NFC antenna matching values — these will be determined on the physical hardware with a VNA;
* changes simply because you personally would have designed something differently.

If the present implementation is electrically sound, please say so.

Optional future improvements are welcome, but they must be clearly separated from anything that actually needs correcting before fabrication.

### Required deliverables

I will provide a structured review package containing the native KiCad project, Gerbers, drills, BOM, CPL, ERC/DRC reports, a detailed review checklist, known design decisions and links to the relevant manufacturer documentation.

I would like the final review to include:

1. A clear overall conclusion:

* safe to fabricate;
* fabricate after listed blockers are corrected; or
* major redesign required.

2. A findings register with each finding classified as:

* **BLOCKER** — must fix before fabrication
* **SIGNIFICANT** — meaningful risk worth addressing
* **RECOMMENDATION** — useful but not required for first articles
* **FIRST-ARTICLE TEST** — should be validated on physical hardware
* **QUESTION** — clarification required

3. For every Blocker or Significant finding:

* exact reference designator / net / location;
* explanation of the potential failure mode;
* recommended correction;
* supporting manufacturer datasheet/application-note page or section where applicable.

4. A short confidence assessment for:

* MCU / USB
* main power
* PoE / power mux
* Ethernet
* ADS1232 / load-cell analogue section
* NFC / RF
* footprints / mechanical
* manufacturing files

5. A final statement answering:
**“If this were your project, would you release these files for manufacture of five first-article boards?”**

### Experience I am looking for

I am specifically looking for somebody with strong real-world PCB/electronics experience, ideally including several of:

* KiCad professional design/review
* ESP32-S3 hardware
* Ethernet PHY / magnetics / W5500 or similar
* IEEE 802.3af PoE
* isolated power
* USB 2.0
* 13.56 MHz NFC/RFID reader design
* RF matching/layout
* precision ADC / bridge sensors / load cells
* mixed-signal PCB layout
* switch-mode power supplies
* PCB DFM / first-article bring-up

A PCB assembler/operator or someone whose experience is primarily basic Arduino PCB layout is unlikely to be suitable for this review.

### When applying

Please answer the following in your proposal:

**1. Will you personally perform the engineering review, or will the work be passed to somebody else?**

**2. What relevant experience do you have with PoE, Ethernet magnetics/PHY layout, NFC/RFID at 13.56 MHz, and precision analogue/ADC design? Please be specific.**

**3. What version(s) of KiCad are you comfortable reviewing professionally?**

**4. Have you previously performed independent pre-fabrication design reviews? Please give an example of the type of defect or risk you have identified on another design.**

**5. Roughly how many engineering hours do you expect a review of this depth to take?**

**6. Can you provide a written findings register with datasheet/application-note references for serious findings?**

**7. Can you complete the review within approximately 3–5 days of receiving the full package?**

Please begin your proposal with the words **“INDEPENDENT PCB REVIEW”** so I know you have read the brief rather than sending a generic bid.

The design files are confidential. They will be provided privately to shortlisted candidates and may only be used for this engineering review.

I am not choosing purely on the lowest bid. I would rather pay an experienced engineer for a thorough review now than manufacture five boards containing the same avoidable design error.