ESP32-S3 System Optimization, budget: 60USDs

******Milestone-Based Contract ******

—-Total project budget is 60 USDs divided over two milestones—-

IMPORTANT: NO PLACEHOLDER BIDS. Generic automated proposals will be immediately declined and reported. To prove you have read and comprehended the complete engineering scope, your proposal MUST start with the exact phrase: HARDWARE-EXPERT --- PROJECT CONTEXT --- We are developing, an industrial-grade, 4-layer ESP32-S3 electronic system designed for continuous 24/7 outdoor operation (-10°C to +65°C ambient, up to 95% RH). NOTE: The schematic architecture and initial KiCad layout already exist (~80% complete). This project is strictly for schematic audit, protection/sensor circuit integration, PDN electrical simulation, 4-layer PCB optimization, 3D CFD thermal validation, and generation of a zero-error production release package. --- SCOPE OF WORK & DELIVERABLES --- ■ Milestone 1: Schematic Audit, Protection Sub-circuits & Electrical/PDN Simulation ($20) 1. Schematic Audit & Component Engineering: • Complete audit of existing KiCad schematic for signal integrity, power stability, and component lifecycle (active MPNs only on DigiKey/Mouser/LCSC; no NRND/EOL). • Power Architecture: Optimize power sequencing across e-Fuse, dual buck converters (12V to 5V & 3.3V), and LDOs to eliminate ESP32 back-powering. 2. Peripheral & Circuit Integration: • Audio Subsystem: Integrate WM8960 audio codec (2x Class-D BTL speaker outputs + 2x differential analog MIC connectors). Resolve ESP32-S3 GPIO mapping conflicts with bootstrapping/flash pins. • Protected JST Connectors: - 1x Illuminated ON/OFF Switch (N-Channel low-side MOSFET + RC debounce + TVS). - 4x Dry-Contact Sensor ports (2-Pin JST with 10k/100nF RC debounce + bidirectional TVS). - 2x Active Sensor ports (3-Pin JST with PTC Polyfuse + 100nF decoupling + TVS). 3. Electrical & PDN Simulation: • Perform transient load, startup analysis, and Power Delivery Network (PDN) impedance optimization using Siemens HyperLynx or LTspice. • Establish Galvanic Isolation strategy and Creepage/Clearance design rules. • M1 Deliverables: Native editable KiCad schematic files, custom libraries, clean ERC Report (0 critical errors), structured BOM with active MPNs, native simulation profiles (.hyp / .asc) with waveform reports, and Isolation Design Note. ■ Milestone 2: 4-Layer PCB Layout, 3D Thermal Simulation & Manufacturing Release Package ($40) 1. 4-Layer PCB Layout Optimization: • 4-layer stackup routing in native KiCad with strict galvanic isolation between AC/DC high-power and low-voltage RF/ESP32 logic. • Audio integrity: Solid continuous ground plane with strict spatial isolation (or dedicated AGND/DGND single star tie) for zero WM8960 noise. • ICT test points on critical rails/signals and auto-reset UART/USB programming interface. 2. 3D Thermal CFD Simulation & Reliability Analysis: • Full 3D Thermal CFD Simulation (ANSYS Icepak or Siemens Simcenter Flotherm) under continuous 24/7 full-load at -10°C to +65°C ambient. • Hotspot mitigation (thermal vias, copper pours, heatsinks). • Formal Component Derating & Arrhenius-based Lifetime Report validating 5+ years 24/7 operational lifespan. 3. Complete Manufacturing Release Package: • Complete Gerber Files (RS-274X/X2), NC Drill, ODB++/IPC-2581 dataset, IPC-D-356 Netlist, and Centroid (Pick & Place) files. • Assembly Drawings, Fabrication Notes (ENIG, IPC Class 2/3), Solder Paste Stencils, and final Production BOM (including 2x IPEX antennas). • Clean DRC Report with ZERO errors. • 3D STEP mechanical model of the fully populated PCBA. • Native thermal CFD project files, high-res simulation video demo, and PDF Thermal Report. • GPIO Mapping Sheet, Bring-up checklist, and Signed Manufacturing Release Checklist. • SI & Impedance Report: HyperLynx SI verification for differential pairs (90Ω USB, 100Ω RS485/HUB75, 50Ω RF). • Panelization & Documentation: Panelized Gerbers (fiducials/mouse-bites), Design Calculations PDF (TVS/fuse sizing, trace ampacity), and Bring-up / Flashing guide. • Design Revision Log & DRC: Formal KiCad revision log and exported HyperLynx DRC / KiCad DRC reports (0 errors). --- COMPLIANCE, IP & NDA --- • Full IP ownership and all native editable source files (KiCad, HyperLynx/LTspice, Icepak, STEP) transfer to the client upon milestone payment. • Formal NDA and standard Design-for-Compliance (DFC) quality warranty apply. Please submit your proposal with examples of past KiCad schematics, multi-layer layouts, and ANSYS/Flotherm thermal simulation reports.