Basic VLSI Circuit Design -- 2

I’m looking for a VLSI-savvy freelancer who can take a simple circuit concept and turn it into a clean, ready-to-fabricate design. The task is firmly in the “basic” range, so I don’t expect multi-million-gate SOC complexity—just a well-thought-out block that follows good layout and timing practices.

Here’s what I need:
• Capture the schematic from my written spec (a brief netlist and functional description will be supplied).
• Produce a layout that meets foundry DRC/LVS rules; Cadence Virtuoso, Mentor, or an open-source alternative is fine as long as you state the PDK you’re comfortable with.
• Supply simulation results that verify the target functionality and basic timing. SPICE, Spectre, or ngspice are all acceptable.
• Provide a concise hand-off package: schematic files, layout GDS/OASIS, simulation decks, and a short report explaining assumptions, corner cases, and any trade-offs made.

I can answer questions quickly and will review each milestone within 24 hours, so communication should be straightforward. If you bring accuracy, clear documentation, and a collaborative spirit, this should be an easy win for both of us.