Verilog RAM Module Design

I need a Verilog-HDL RAM module that meets an already defined specification. The core requirement is a synchronous memory unit with reliable read/write control. Beginning from the RTL, I want clean, synthesizable code, followed by a self-checking testbench that proves functional correctness across corner cases.

Your workflow should include:
• RTL implementation of the RAM with parameterised depth and width
• A functional testbench that drives realistic stimuli and automatically flags mismatches
• Simulation runs in ModelSim or an equivalent simulator, with waveform capture for review
• Iterative debugging until the waveforms reflect the expected behaviour
• Concise documentation explaining interface signals, timing, and any design decisions

Address decoding and error-correction features are not mandatory right now, but keep the architecture open so they could be added later without a rewrite.

Deliverables will be the synthesizable Verilog source, the testbench, simulation scripts, a short PDF or Markdown report, plus all generated waveform files. Once the testbench passes and I can reproduce the results locally, the project is complete.