Tiny Tapeout Project Submission Help

I’m preparing a project for the next Tiny Tapeout run and want a freelancer who has already gone through the full flow—design capture, simulation, verification, and the YAML-based submission—so I can be confident everything lands in the shuttle without last-minute surprises.

note: the freelancer should have background VLSI/ASIC.

Where I am today
• My concept is defined, but I’m flexible on the implementation path.
• I have no blockers on tool choice; whether you prefer Verilog/SystemVerilog, OpenLane, KLayout, or the official Tiny Tapeout CLI, I’m happy to follow your proven workflow.

What I’d like you to cover
1. Review or help create the RTL/netlist so it meets Tiny Tapeout’s size and pin-count limits.
2. Build the required testbench, run simulations, and prove it passes the tt-test automated checks.
3. Package the design (gds, json, sv, png, tt.yaml) and walk me through the GitHub submission so the project is accepted by the CI pipeline.
4. Leave me with clear notes on how to reproduce the flow for future revisions.
5. create a PCB testing chip I will explain what it should do.

Acceptance criteria
• The GitHub pull request passes all Tiny Tapeout automated checks.
• I receive the final GDS and supporting files in a tagged release.
• A concise walkthrough document (or screencast) shows each step from clone to successful make lf.

If you have a Tiny Tapeout chip already in silicon or can point me to a project you shepherded through the shuttle, that will carry a lot of weight. Let’s get this little chip taped out together!