SystemVerilog UVM Functional Verification

The RTL is already stable and synthesizable; my focus now is to complete functional verification using SystemVerilog within an existing UVM environment. The current testbench boots and runs smoke tests, but coverage is sitting at roughly 65 %.

What I need done
• Extend the UVM environment: add agents, sequences, and scoreboards where gaps exist.
• Build a self-checking regression suite that targets corner cases specified in the design spec.
• Integrate functional coverage points and deliver closure to > 95 % line, toggle, and cross coverage.
• Debug failing tests and provide concise root-cause reports and fixes or waivers.
• Produce a final deliverable package containing all source, scripts, and a reproducible regression run.

Acceptance criteria
– All regressions run clean on Mentor Questa or Synopsys VCS (your choice, provide MAKE/Do files).
– Coverage reports generated by the simulator show ≥ 95 % for all defined metrics.
– Scoreboards and checkers flag no unexpected mismatches over a 24-hour stress run.

SystemVerilog, UVM, functional coverage collection (UCDB/HTML), and scripted regressions (Python, Make, or similar) should be second nature for you. Continuous communication over Git or Perforce and weekly progress summaries will keep the project on track.