Solar Carrier PCB Layout, DFM & BOM

PCB Layout + DFM + Production BOM — Solar Carrier Board (4-layer, industrial)
Project summary
I have a fully engineered carrier PCB for a solar-powered, battery-backed sensor board used in open paddocks. The schematic design work is complete. I need an experienced layout engineer to take it to fabrication-ready outputs for JLCPCB.

The board:

Approx. 110 x 85 mm, 4-layer (SIG / GND / PWR / SIG), 1 oz outer copper minimum (2 oz acceptable if it helps the power paths)
Sealed IP65 pole-mounted enclosure, no forced air, -20 C to +65 C internal, conformal coated, condensing humidity
Designed to industrial tier margins throughout — this is not a hobby board and it will live outdoors on a livestock crush for years
Functional blocks on the board:

Solar MPPT charger — CN3722 buck charger for a 4S LiFePO4 12 V pack, external P-FET high side, coordinated two-stage 22 V surge clamp, reverse-polarity protection on both solar and battery, serviceable 5 A fuse, pack NTC cold-charge inhibit
System power — TPS54260 60 V buck (VBAT to +5 V, 2 A) plus a low-noise LDO to +3V3, battery voltage sense divider
MCU carrier — two 1x18 2.54 mm sockets for a plug-in Heltec WiFi LoRa 32 V4 module (module is not soldered; it plugs in)
Dual load-cell front end — two independent NAU7802 24-bit bridge ADCs on two separate I2C buses, with a low-noise 2.8 V ratiometric excitation LDO. Full-scale bridge signal is 5.6 mV — these are the most noise-critical nets on the board
Dual RS-485 RFID reader ports — SN65HVD72 transceivers, plus per-port GPIO-switched 12 V reader feeds (discrete P-FET high side + PPTC + series blocking Schottky), full TVS/series-resistor protection
Field tare pushbutton input — debounced, ESD protected
Field I/O: 5.08 mm pluggable screw terminals for solar, battery, two load cells, two reader ports, tare button, plus an M4 chassis earth stud.

What is already complete (you are not designing the circuit)
Complete, validated schematic package for all six blocks, with a fully resolved netlist
Every component selected, with MPN and LCSC part number already assigned
Footprints assigned for every non-primitive part
Four separate ground domains (PGND, DGND, AGND, CHASSIS) with the single-point bond location for each pair already specified and owned by a named block
27 test points specified with exact net, purpose and placement rules
Written DFM constraints per block: minimum trace widths per rail (IPC-2221 derived), via sizes, creepage, silkscreen rules
Power budget, thermal assumptions and protection coordination all documented
Firmware/strapping-pin constraints documented (relevant to you only as "do not move these nets")
You will receive the schematics, netlist, BOM with LCSC codes, the constraint list, and the mechanical/enclosure requirements.

What I need you to deliver
1. PCB layout and routing to the supplied constraint set, including:
A signal-integrity/thermal sanity review as a deliverable
4-layer stackup definition and impedance targets
120 ohm differential pairs for both RS-485 ports (length matched within 5 mm, ports >= 5 mm apart)
Tight, guarded differential pairs for both load-cell signal pairs, length matched within 2 mm, over a continuous AGND island, >= 10 mm from any switching node, never adjacent to a switching plane
Two switching loops kept tight: CN3722 power loop under ~15 mm perimeter, buck input loop under ~10 mm perimeter, both with solid PGND pour beneath
Correct ground-domain partitioning with the three specified single-point bonds implemented exactly as specified — no accidental second path between domains
Power trace widths per the supplied table (solar/battery >= 2.5 mm, VBAT >= 1.7 mm, +5 V >= 1.0 mm, etc.)
>= 1.5 mm creepage on every net above 12 V, pollution degree 3
Field terminals arranged on the board edge for cable gland access, with the tare terminal deliberately separated from the 12 V reader terminals
Every terminal position and every test point silkscreen labelled in >= 1.0 mm text, pin-1 markers on both Heltec sockets, and every Heltec socket position labelled with its signal name
Four M3 mounting holes, >= 3 mm keep-out around the seated Heltec module, LoRa antenna connector and USB-C port left accessible
2. Clean DFM pass at JLCPCB. Not "probably fine" — I want the layout run against JLCPCB's current capability set and returned with zero DFM warnings and zero DRC errors, plus the DFM report as evidence. If a constraint in my package conflicts with JLCPCB capability, flag it to me rather than silently relaxing it.

3. Complete production BOM, verified in stock at JLCPCB. This is a hard deliverable, not a formality:

Every line item confirmed currently in stock at JLCPCB in the quantity required for a first build of 5 boards, with stock figures and the date checked
Basic-tier parts preferred for all generic R/C/L and commodity discretes; the Extended-tier lines are already identified and approved
I have a do-not-substitute list (the charger, ADCs, RS-485 transceivers, buck, both low-noise LDOs, three precision passive groups, and the reader high-side switch topology). These are locked. Any other substitution must match rating, package, polarity and pin order, and be listed for my approval
Clearly flag any part that is out of stock, EOL, or extended-lead-time, with a proposed drop-in alternative
Deliver as a JLCPCB-format BOM and CPL/pick-and-place file, ready to upload
4. Fabrication and assembly outputs: gerbers, drill files, netlist export, assembly drawings, 3D model (STEP) for enclosure fit check, and the source project files.

Skills I am looking for
Demonstrable mixed-signal layout experience — you understand why a 5.6 mV bridge signal and a switching charger cannot share a return path
Real experience with split ground domains and single-point bonding
Proven track record of boards that went to JLCPCB and came back clean and assembled first time
Outdoor/industrial hardware experience is a strong plus
To apply
Please include:

Two examples of mixed-signal or power boards you laid out, ideally 4-layer, ideally manufactured at JLCPCB — with a brief note on what the noise-critical constraint was and how you handled it
Your CAD tool of choice (KiCad preferred; state clearly if you work in Altium and how you'd hand off)
Your fixed price for the full scope above, and your realistic timeline
A one-line answer to this: what is the first thing you check when a board has both a switching charger and a 24-bit bridge ADC on it?
Please do not send generic proposals. I will only read applications that reference specifics from this brief.

Milestone 1: Placement approval / routing complete.
Milestone 2: DFM-clean outputs + BOM