Senior Design Verification Mentor

I am a junior design-verification engineer working on projects that rely heavily on UVM and SystemVerilog. The scope of my day-to-day work shifts—from setting up testbenches and drafting verification plans to digging through waveforms when bugs appear—so I’m looking for an experienced engineer who can step in whenever a challenge arises.

Here’s what I need from you:

• On-demand problem-solving whenever I hit a roadblock, whether the issue is in stimulus generation, coverage closure, or a stubborn simulation mismatch.
• Broader guidance and mentorship that helps me grow: reviewing my overall approach, suggesting best practices, and explaining why a particular methodology choice matters.

Code reviews are welcome when time permits, but the primary focus is quick, insightful troubleshooting and strategic advice that I can immediately apply to upcoming tasks.

If you have a strong background in UVM testbench architecture, SystemVerilog assertions, and the typical debug flow on popular simulators, your expertise will make a direct impact on both my current assignments and my professional development. Let’s connect so I can outline the next task in detail and arrange a schedule that fits us both.