RTL-to-GDSII Design Support

I have a new digital IC project that must be driven all the way from a production-ready RTL hand-off to a clean, sign-off GDSII database ready for tape-out. Your role is to own that backend flow: translate the existing RTL into a manufacturable layout, validate it against foundry rules, and package the documentation I need for final submission.

Because this is an end-to-end engagement, I will rely on you to select and configure the right EDA tool chain (Synopsys, Cadence, Siemens, or a comparable stack) and to steer each stage—logic synthesis, floor-planning, place-and-route, timing closure, power analysis, DRC/LVS, formal equivalence, and final GDSII generation—until all sign-off criteria are met. Expect close collaboration with our internal front-end and verification teams; the RTL is stable, but we value iterative feedback to catch corner-case issues early.

Deliverables
• Clean, sign-off GDSII and all intermediate databases
• Reports for STA, power, DRC, LVS, ERC, and formal equivalence
• A brief implementation log outlining major decisions, tool versions, and scripts

Acceptance will be based on passing foundry sign-off decks (to be supplied after kickoff) with zero critical violations and timing closure at the agreed PVT corners.

If you have taped out chips before and are comfortable owning the complete RTL-to-GDSII flow, I’d like to discuss schedules and your preferred tool environment.