PCB Design Engineer — Finish & Validate a 4-Layer Sensor Board (KiCad, JLCPCB)

PCB Design Engineer — Finish & Validate a 4-Layer Sensor Board (KiCad, JLCPCB)

Type: Fixed-price or hourly, short engagement (est. 1–2 weeks of focused work)
Tools: KiCad 10.x (project files provided), JLCPCB fab/assembly

Overview

We have a 112mm round, 4-layer, sealed/IP67, battery-powered wireless sensor board (built around an ESP32-S3 module) for a sports-court sensor system. The design is largely complete: schematic captured, board placed and routed across all 4 layers (F.Cu / GND plane / POWER plane / B.Cu), DRC-clean against JLCPCB's fab-floor rules, and most components matched to real, in-stock LCSC part numbers with a JLCPCB-format BOM and CPL/position file already prepared.

We need an experienced PCB/hardware engineer to (1) independently review and validate the existing design before we commit to fab, and (2) close out two specific open items described below.

Scope of work

1. Design review / sign-off
- Review the schematic and board for correctness: power architecture (battery charging, buck-boost 3.3V rail, 5V boost rail), USB-C power/data wiring, ESD/TVS protection placement and net coverage, I2C bus (fuel gauge + accelerometer), and the addressable LED ring driver.
- Independently re-run DRC (JLCPCB constraints: 0.127mm min clearance/trace width, 0.2mm min via drill) and sanity-check the ~195 disclosed sub-optimal-but-passing clearance findings in saturated routing areas — confirm none of them are actually load-bearing risks.
- Flag anything you'd change before this goes to a paid fab run.

2. USB-C connector needs a real footprint swap (open item)
- The currently-drawn USB-C receptacle (LCSC C2894897) turnet all on closer inspection of its datasheet, despite thedesign requiring a sealed connector.
- We've identified a genuinely IP67-rated, LCSC-stocked replG-SMT-TR-67 (LCSC C3197945) — a 24-pin USB 3.2 Gen2 shellthat's pin-compatible with our 16 used signals (8 unused SuperSpeed pins go no-connect).
- Needs: a new KiCad footprint authored from the real datashfferent pad pitch and THT-anchored shell legs vs. the currentpart), re-placement at the board edge (there's a pre-cut flat chord in the round outline for the connector), and DRC/clearance re-verification —
including keep-out clearance to the MCU module's antenna a

3. Battery charger + fuel gauge PCB placement (open item)
- Two ICs (a Li-ion/LiFePO4 charger and an I2C fuel gauge) had their schematic symbols corrected to match their real chosen parts' full pinouts, but
the PCB-side footprint swap is still blocked by genuine sp of the board — including a discovered short risk between one part's exposed thermal pad and a nearby power trace.
- Needs: a real placement/routing solution for both parts in(may require local re-routing of neighboring nets), verifiedDRC-clean, no compromise on the thermal pad clearance.

Deliverables

- Updated KiCad 10.x project (schematic + PCB) with both open items resolved
- A short written review note: anything you found or changed
- Updated BOM/CPL for JLCPCB reflecting any part changes
- Fresh DRC report showing the final state clean (or with ancitly justified)

What we're looking for

- Real experience taking a board through DRC to fab, ideally
- Comfortable authoring KiCad footprints directly from manufacturer mechanical drawings/datasheets
- Some familiarity with battery charging circuits (charge/saadjacent layout (keep-out zones near an antenna)
- Please include: relevant past board examples (photos or gerbers fine), and your estimated turnaround for the scope above