KiCad RF Zynq PCB Cleanup
Budget / Salary$30–250
TypeFreelance project
LocationRemote
Posted2 hours ago
Project Title:
Expert KiCad 10.0 PCB Engineer – 4-Layer RF, Zynq XC7Z020 & Dual AD9361 Layout Cleanup
Project Description:
Looking for an experienced PCB layout engineer to finish routing and resolve DRC violations on a 4-layer RF board in KiCad 10.0.
Board Specifications:
Stackup: 4 layers (F.Cu, In1.Cu, In2.Cu, B.Cu), 0.6234 mm board thickness, 277 footprints.
Key Components: Xilinx Zynq XC7Z020 SoC (BGA), two AD9361 RF transceivers (BGA), and DDR3 memory (BGA).
Current Status: ~499 unrouted ratsnest nets and 449 DRC errors remaining after partial cleanup.
Scope of Work:
Route remaining power, signal, and RF nets.
Fix RFGND copper pour boundary shorts encroaching on RF pads.
Resolve crossing tracks (including U6 RX stub shorting into resistor pads) and power rail track-to-via shorts (VCC_1V8, VCC_1V5, DDR3_VREF).
Clear all remaining BGA clearance violations to achieve 0 DRC errors for Gerber export.
Strict Constraints:
50-ohm controlled impedance on RF traces, differential pairs on AD9361 RX/TX lines, and DDR3 length matching.
Component placements are locked; existing tracks/vias cannot be moved or deleted without approval.
To Apply (Mandatory):
Please confirm your experience with Xilinx Zynq XC7Z020, AD9361, and DDR3 in KiCad, and attach 2–3 layout/3D screenshots of similar high-speed RF/BGA boards you have routed. Generic proposals without screenshots will not be considered.
Expert KiCad 10.0 PCB Engineer – 4-Layer RF, Zynq XC7Z020 & Dual AD9361 Layout Cleanup
Project Description:
Looking for an experienced PCB layout engineer to finish routing and resolve DRC violations on a 4-layer RF board in KiCad 10.0.
Board Specifications:
Stackup: 4 layers (F.Cu, In1.Cu, In2.Cu, B.Cu), 0.6234 mm board thickness, 277 footprints.
Key Components: Xilinx Zynq XC7Z020 SoC (BGA), two AD9361 RF transceivers (BGA), and DDR3 memory (BGA).
Current Status: ~499 unrouted ratsnest nets and 449 DRC errors remaining after partial cleanup.
Scope of Work:
Route remaining power, signal, and RF nets.
Fix RFGND copper pour boundary shorts encroaching on RF pads.
Resolve crossing tracks (including U6 RX stub shorting into resistor pads) and power rail track-to-via shorts (VCC_1V8, VCC_1V5, DDR3_VREF).
Clear all remaining BGA clearance violations to achieve 0 DRC errors for Gerber export.
Strict Constraints:
50-ohm controlled impedance on RF traces, differential pairs on AD9361 RX/TX lines, and DDR3 length matching.
Component placements are locked; existing tracks/vias cannot be moved or deleted without approval.
To Apply (Mandatory):
Please confirm your experience with Xilinx Zynq XC7Z020, AD9361, and DDR3 in KiCad, and attach 2–3 layout/3D screenshots of similar high-speed RF/BGA boards you have routed. Generic proposals without screenshots will not be considered.
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