KiCad PCB Routing Completion

### What this is

I have three KiCad 10 boards for a telecom cabinet monitoring and access-control
product. Schematic capture, part selection, footprints, placement, design rules,
BOM and fabrication output are all finished. One board is fully routed. The other
two have a short list of connections that two autorouters could not place, and I
need an experienced layout engineer to close them by hand.

This is **not** a "design my PCB" job. It is a well-defined finishing task on a
board that is already DRC-clean, with every remaining connection documented and its
obstacle identified.

### Current state, measured

| Board | Size | Layers | DRC errors | Connections open |
|---|---|---|---|---|
| Base | 155 × 90 mm | 4 | 0 | 23 |
| Cellular module | 80 × 85 mm | 4 | 0 | 0 — complete |
| Battery module | 105 × 80 mm | 2 | 0 | 11 |

The base board carries 196 components, 160 nets, 546 SMD pins, 2661 track segments
and 358 vias. `In1.Cu` is a solid, uncut ground plane and carries zero track
segments; keeping it that way is a hard requirement (see constraints).

### Scope of work

1. Close the 23 open connections on the base board and the 11 on the battery module.
2. Finish with **zero error-severity DRC violations** on all three boards, using the
project's own rules as supplied. No rule edits.
3. `In1.Cu` still carrying zero track segments on the base board, verifiable with a
one-line script I provide.
4. Every track at or above its net class width, verifiable with a script I provide.
5. A short written note for any connection you could not close, saying what you
tried and what blocked it. A documented open connection is an acceptable
deliverable; an undocumented one is not.

If closing a connection genuinely requires moving a component, that is allowed for
passives, with the move and the reason noted. A list of parts that must not move is
in the handover pack.

### What makes the remaining connections hard

I want you to see this before bidding, because it is the actual difficulty.

- **12 are fine-pitch escapes.** The accelerometer `U7` has 0.15 mm between its own
pads. `U14` is 0.25 mm, `U12`/`U13` 0.30 mm, `U1`/`U2` 0.35 mm. The board has
generated per-part pin-escape rules permitting 0.13 mm clearance and a 0.20 mm
width floor inside those footprints' courtyards, so the escapes are legal — they
just need doing carefully. One connection runs between two pins of `U7` itself and
may not be possible; say so if it is not.
- **5 are in the 46–60 V input section**, in the `HV` net class at 0.40 mm track and
0.60 mm clearance (IPC-2221 Table 6-1, category B2, 51–100 V band). That needs
1.60 mm to pass between two things, in the most crowded part of the board.
`/HV_SW` and `/HV_BST` are switching nodes and should be kept short and compact.
- **6 are plain congestion** on relay-to-terminal and auxiliary-loop nets. These are
ordinary work.
- **9 of the battery module's 11** are escapes at the charger (`U1`, 0.20 mm pad gap)
and the current monitor (`U3`, 0.15 mm).

### Hard constraints

These are the ones that will get work rejected if ignored:

- **Do not route on `In1.Cu`.** It is the ground reference plane for every signal on
`F.Cu` and the reason the board is four layers. KiCad cannot express this as a
design rule, so DRC will not stop you — it is checked separately and it is checked.
Stitching vias *to* the plane are fine and encouraged.
- **Do not edit the design rules, net classes, or the `.kicad_dru`.** They are
generated from measurements and from IPC-2221, and both the net class and the
custom rule files are regenerated by scripts, so hand edits are lost anyway.
- **Do not widen or narrow a track outside its class**, except the permitted neck-down
inside a pin-escape courtyard.
- **Do not move** the ESP32 module `U6` (its antenna keep-out currently hangs off the
board edge), the 15 field-wiring terminals, the HV switching regulator group, or
any decoupling capacitor sitting beside a supply pin.
- **Open the project (`.kicad_pro`), not the bare `.kicad_pcb`.** The rules live
beside the board. Opening the board alone gives you one default net class and no
custom rules, and DRC will then report clean against rules that are not this
board's.

### Required skills

- KiCad 9 or 10 PCB editor, fluent. Interactive router, push-and-shove, layer
management, DRC.
- Real experience routing fine-pitch QFN and MSOP escapes at 0.15–0.35 mm pad gaps.
- Comfortable reading a custom `.kicad_dru` with `intersectsCourtyard` conditions.
- Git, at a basic level: clone, branch, commit, push. Work is handed back as commits
on a branch, not as a zip of files.

Nice to have: experience with 46–60 V telecom supply sections and creepage practice.