KiCad PCB Layout Engineer: 2-Layer ESP32 Battery-Powered Board (Spec & BOM Provided)
Budget / Salary₹1,500–12,500
TypeFreelance project
LocationRemote
Posted1 hour ago
We are looking for an experienced KiCad PCB layout engineer to design and route a compact, battery-efficient 2-layer ESP32-WROOM-32E board for our smart IoT device.
We have already completed the circuit engineering, component selection, net map, and mechanical envelope. You will be provided with:
1. A comprehensive 19-page PDF Engineering Specification with exact pinouts, power topologies, and routing rules.
2. A complete Excel BOM with exact footprint definitions, component MPNs, and Indian distributor references.
3. Legacy KiCad board files containing the exact board outline (52.98 mm × 34.00 mm with stepped corner) and coordinates for 6 mechanically locked components.
SCOPE OF WORK:
1. Schematic Capture / Verification in KiCad 7 or 8:
- Implement clean schematic matching our provided PDF specification and net map.
- Core ICs: ESP32-WROOM-32E, ME6211C33 (3.3V LDO), MT3608 (5V Boost), AO3401A P-FETs (power gating), 2N7002 N-FETs (gate drivers), and SN74AHCT1G125 (5V RGB logic buffer).
- Resolve series control resistor nets so both sides have distinct net names for DRC enforcement.
2. 2-Layer PCB Layout & Routing:
- Mechanical Enclosure Match: Exact preservation of board outline, internal 2.0 mm cutout, and 6 locked component footprints/layers (Pushbutton, Programming Header, RTC Header, Slide Switch, Buzzer, and RGB Connector).
- ESP32 RF Performance: Enforce strict antenna keepout (no copper, vias, or traces on BOTH top and bottom copper layers).
- Power Stage: Compact MT3608 switching loop (SW node minimal area); wide power tracks (≥1.2 - 1.5 mm or copper pours) for high-current battery/servo rails.
- Solid Bottom Ground Plane: Maintain an uninterrupted ground plane on the bottom layer with proper stitching vias.
3. Design Rules & DRC Sign-Off:
- Zero ERC errors and zero DRC errors in native KiCad.
- Verification against real manufacturer footprints/datasheets.
DELIVERABLES:
1. Complete, editable KiCad 7/8 source project (.kicad_pro, .kicad_sch, .kicad_pcb, and local footprint/symbol libraries).
2. Production-ready Gerber RS-274X package + Excellon NC drill files (fab-ready for JLCPCB/PCBWay).
3. Pick-and-Place (CPL / Centroid) CSV file and Assembly BOM.
4. High-resolution PDF schematic and 3D board renders (top/bottom).
5. Mechanical verification screenshot demonstrating 100% overlay alignment of the 6 locked parts with the legacy board.
QUALIFICATIONS REQUIRED:
- Proven experience with battery-powered ESP32 boards, switching converters, and RF layout.
- Fluent in KiCad 7 or 8.
- Attention to detail with design rule checks (DRC).
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BOT / SPAM FILTER (MANDATORY):
To prove you read this entire description, start your bid proposal with the exact word: "BOTURO-REV-D" and answer this quick question: "Which pin of the ME6211C33 SOT-23-5 regulator is Ground?" Proposals without this keyword and answer will be automatically declined.
We have already completed the circuit engineering, component selection, net map, and mechanical envelope. You will be provided with:
1. A comprehensive 19-page PDF Engineering Specification with exact pinouts, power topologies, and routing rules.
2. A complete Excel BOM with exact footprint definitions, component MPNs, and Indian distributor references.
3. Legacy KiCad board files containing the exact board outline (52.98 mm × 34.00 mm with stepped corner) and coordinates for 6 mechanically locked components.
SCOPE OF WORK:
1. Schematic Capture / Verification in KiCad 7 or 8:
- Implement clean schematic matching our provided PDF specification and net map.
- Core ICs: ESP32-WROOM-32E, ME6211C33 (3.3V LDO), MT3608 (5V Boost), AO3401A P-FETs (power gating), 2N7002 N-FETs (gate drivers), and SN74AHCT1G125 (5V RGB logic buffer).
- Resolve series control resistor nets so both sides have distinct net names for DRC enforcement.
2. 2-Layer PCB Layout & Routing:
- Mechanical Enclosure Match: Exact preservation of board outline, internal 2.0 mm cutout, and 6 locked component footprints/layers (Pushbutton, Programming Header, RTC Header, Slide Switch, Buzzer, and RGB Connector).
- ESP32 RF Performance: Enforce strict antenna keepout (no copper, vias, or traces on BOTH top and bottom copper layers).
- Power Stage: Compact MT3608 switching loop (SW node minimal area); wide power tracks (≥1.2 - 1.5 mm or copper pours) for high-current battery/servo rails.
- Solid Bottom Ground Plane: Maintain an uninterrupted ground plane on the bottom layer with proper stitching vias.
3. Design Rules & DRC Sign-Off:
- Zero ERC errors and zero DRC errors in native KiCad.
- Verification against real manufacturer footprints/datasheets.
DELIVERABLES:
1. Complete, editable KiCad 7/8 source project (.kicad_pro, .kicad_sch, .kicad_pcb, and local footprint/symbol libraries).
2. Production-ready Gerber RS-274X package + Excellon NC drill files (fab-ready for JLCPCB/PCBWay).
3. Pick-and-Place (CPL / Centroid) CSV file and Assembly BOM.
4. High-resolution PDF schematic and 3D board renders (top/bottom).
5. Mechanical verification screenshot demonstrating 100% overlay alignment of the 6 locked parts with the legacy board.
QUALIFICATIONS REQUIRED:
- Proven experience with battery-powered ESP32 boards, switching converters, and RF layout.
- Fluent in KiCad 7 or 8.
- Attention to detail with design rule checks (DRC).
---
BOT / SPAM FILTER (MANDATORY):
To prove you read this entire description, start your bid proposal with the exact word: "BOTURO-REV-D" and answer this quick question: "Which pin of the ME6211C33 SOT-23-5 regulator is Ground?" Proposals without this keyword and answer will be automatically declined.
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