KiCad DSP-SDRAM Trace Optimization

My current KiCad 10 board is designed, but the differential traces that connect the DSP to the external SDRAM are not length-matched or impedance-controlled. I need the layout reviewed and re-routed so those critical nets meet the timing budget of the processor.

Scope
• Analyse the existing PCB to identify every DSP↔SDRAM signal that exceeds length or impedance targets.
• Re-route or tune the traces inside KiCad so data, address, and control lines are matched within the manufacturer-specified tolerance.
• Adjust layer stack-up, via strategy, or termination as required to achieve 50 Ω single-ended / 100 Ω differential (or the closest feasible value based on the current stack-up).
• Update the constraints in the KiCad design rules so future edits stay compliant.
• Provide simulation or measurement evidence (KiCad’s built-in impedance calculator, Saturn PCB, or an IBIS-based tool of your choice) that the new routing resolves the timing issue.

Deliverables
1. Revised .kicad_pcb file with clean DRC.
2. A brief report outlining what was changed, the final trace lengths/impedances, and confirmation that the DSP and SDRAM timing margins are now met.
3. Any scripts, constraint files, or calculation sheets used during the optimisation.

Acceptance Criteria
• All critical nets within ±10 mil length skew (or tighter if achievable).
• Impedance of each net proven to be within ±10 % of target.
• No new ERC/DRC errors introduced.

This is a focused task on a single board spin, so efficient turnaround and clear documentation are key.