IMXRT1064 Prototype PCB Design & Schematics
Budget / Salary€200–400
TypeFreelance project
LocationRemote
Posted2 hours ago
I’m looking for a complete, production‑ready schematic and a four‑layer PCB layout for a feature‑rich prototype built around NXP’s i.MX RT1064. The board will be used to run game emulators (PSX, NES, SNES) and a custom OS designed for Cortex‑M microcontrollers.
The design can be largely based on the MIMXRT1060 EVK, with modifications listed below.
This is an engineering validation platform only, so the priorities are signal integrity, correct high‑speed routing, and ease of probing. Aesthetics are not important.
Target board size: 150 × 80 mm, or 150 × 120 mm if routing density requires it. Main buck converter can be TPS563201 as i got them quiet a lot and SMT components in 0603 package are preferrable.
Display to be connected (pinout in listing):
https://pl.aliexpress.com/item/1005009736441514.html
Key silicon and interfaces already selected:
• 2 Gb MX25UM2G45G Octal-SPI flash
• 4x IS42RM16160K SDRAMs (32-bit bus)
• 40-pin RGB LCD header plus 6-pin GT911 touch FPC
• ESP32 WROOM32 acting solely as a Bluetooth bridge (UART or SPI link to RT1064)
• KSZ8081 PHY for 10/100 Ethernet (RJ-45)
• Dual USB - one full-speed device, one high-speed host
• WM8960 codec feeding a 3.5-mm jack
• microSD slot, 4-position DIP boot selector, standard 10-pin JTAG, and USB-C input for 5 V power
I’ll provide component datasheets and any NXP reference material you might need. The rest - including pin-mux choices(TBD), power tree, impedance-controlled stack-up, and high-speed length matching - are in your hands.
Deliverables expected:
1. Complete schematic in Altium, KiCad or Proteus, error-free ERC/DRC
2. PCB layout meeting the size constraint with controlled impedance tracks for SDRAM, USB HS, and RGB lines
3. Manufacturing outputs: Gerbers, drill files, pick-and-place, and a clearly costed BOM
4. PDF plot of schematics & assembly drawings for quick review
5. Brief design report highlighting power domains, DDR timing strategy, and any constraints that drove the final topology
The project is considered complete once the design loads cleanly, passes your DRC, and Gerbers generate without issues.
This is a hobby project, so I’m flexible and open to negotiation regarding price.
If everything works well, I’ll happily share the complete board + software with you.
Feel free to contact me - looking forward to working together. Regards.
The design can be largely based on the MIMXRT1060 EVK, with modifications listed below.
This is an engineering validation platform only, so the priorities are signal integrity, correct high‑speed routing, and ease of probing. Aesthetics are not important.
Target board size: 150 × 80 mm, or 150 × 120 mm if routing density requires it. Main buck converter can be TPS563201 as i got them quiet a lot and SMT components in 0603 package are preferrable.
Display to be connected (pinout in listing):
https://pl.aliexpress.com/item/1005009736441514.html
Key silicon and interfaces already selected:
• 2 Gb MX25UM2G45G Octal-SPI flash
• 4x IS42RM16160K SDRAMs (32-bit bus)
• 40-pin RGB LCD header plus 6-pin GT911 touch FPC
• ESP32 WROOM32 acting solely as a Bluetooth bridge (UART or SPI link to RT1064)
• KSZ8081 PHY for 10/100 Ethernet (RJ-45)
• Dual USB - one full-speed device, one high-speed host
• WM8960 codec feeding a 3.5-mm jack
• microSD slot, 4-position DIP boot selector, standard 10-pin JTAG, and USB-C input for 5 V power
I’ll provide component datasheets and any NXP reference material you might need. The rest - including pin-mux choices(TBD), power tree, impedance-controlled stack-up, and high-speed length matching - are in your hands.
Deliverables expected:
1. Complete schematic in Altium, KiCad or Proteus, error-free ERC/DRC
2. PCB layout meeting the size constraint with controlled impedance tracks for SDRAM, USB HS, and RGB lines
3. Manufacturing outputs: Gerbers, drill files, pick-and-place, and a clearly costed BOM
4. PDF plot of schematics & assembly drawings for quick review
5. Brief design report highlighting power domains, DDR timing strategy, and any constraints that drove the final topology
The project is considered complete once the design loads cleanly, passes your DRC, and Gerbers generate without issues.
This is a hobby project, so I’m flexible and open to negotiation regarding price.
If everything works well, I’ll happily share the complete board + software with you.
Feel free to contact me - looking forward to working together. Regards.
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