I need custom FPGA firmware for my PCIe DMA board -

I am looking for an experienced FPGA/PCIe developer to develop custom firmware for an existing **PCIe FPGA/DMA board**.

The project is for controlled hardware-security research. The board will be installed in dedicated Intel and AMD test systems to study PCIe endpoint behaviour, DMA security, device/driver interaction, and the methods used by security software to inspect and classify PCIe hardware.

### Project Objective

The goal is to develop a stable, standards-compliant PCIe endpoint with properly implemented and testable device functionality.

The implementation should cover:

* PCIe configuration space
* Functional BARs and register interfaces
* PCIe capability structures
* MSI/MSI-X interrupts
* Correct interrupt generation and handling
* PCIe TLP processing
* Host-to-device communication
* Device-to-host communication
* DMA engine functionality for controlled laboratory testing
* Device initialization and reset behaviour
* Windows 10/11 enumeration
* Device/driver association
* Diagnostic and debugging interfaces

The endpoint should behave consistently when inspected by standard PCIe, Windows driver, and hardware diagnostic utilities.

### Security & Detection Research

An important part of the project is studying how security software recognizes and evaluates FPGA/DMA PCIe endpoints.

Testing will include environments containing kernel-level security and anti-cheat products such as:

* FACEIT Anti-Cheat
* Riot Vanguard (VGK)
* ACE
* Comparable endpoint/device monitoring solutions
* DRV Scan and related driver/device diagnostic tools

The purpose of these tests is to determine what information these products can observe from the PCIe endpoint and which characteristics may cause the hardware to be classified or flagged.

Testing should document:

* Whether FACEIT/VGK/ACE generates a hardware or device-related detection
* Observable differences between the FPGA endpoint and reference hardware
* DRV Scan status and the technical reason behind reported results
* Configuration-space validation
* BAR behaviour and probing
* PCIe capability-chain validation
* Interrupt and ISR behaviour
* MSI/MSI-X operation
* Driver/device correlation
* Device initialization behaviour
* TLP behaviour
* DMA activity visible to the operating system/security environment

The firmware should preferably be modular so individual PCIe characteristics can be changed independently and the resulting detection behaviour compared.

The research objective is **measurement, comparison, documentation, and standards compliance**. Successful bypass of anti-cheat/security software or manipulation of DRV Scan results is not an acceptance requirement.

### DMA Research Functionality

For dedicated systems under my control, the platform should support:

* Controlled DMA reads
* Controlled DMA writes
* Memory acquisition for analysis
* Interrupt-generation experiments
* Configurable DMA test patterns
* PCIe/TLP logging
* BAR/register diagnostics
* Device authentication/DNA locking where supported

Safety controls should be included where practical to prevent accidental access outside configured test ranges.

### Deliverables

1. Complete FPGA source/project files
2. Reproducible build scripts/project configuration
3. Flash-ready FPGA bitstream
4. Host-side test and diagnostic utilities
5. Windows 10/11 driver components where required
6. Detailed build instructions
7. Flashing and recovery instructions
8. Configuration-space documentation
9. BAR/register map
10. PCIe capability documentation
11. Interrupt/MSI/MSI-X documentation
12. Description of DMA and TLP architecture
13. Documentation of security/detection testing results

### Demonstration / Validation

The completed implementation should demonstrate:

* Clean PCIe enumeration
* Configuration-space access
* Functional BAR communication
* Host-to-device communication
* Device-to-host communication
* DMA read/write functionality in the controlled test environment
* Interrupt generation
* Correct driver/device interaction
* Stable operation on the agreed test hardware
* DRV Scan diagnostic results with an explanation of any reported findings
* Documented observations from FACEIT/VGK/ACE testing

### Preferred Experience

Relevant experience includes:

* FPGA PCIe endpoint development
* FPGA-based DMA hardware
* PCILeech/LeechCore-compatible architectures
* Xilinx 7-Series / UltraScale PCIe
* Intel/Altera PCIe IP
* PCIe configuration-space implementation
* BAR/register design
* PCIe TLP processing
* MSI/MSI-X
* DMA engines
* Windows kernel drivers
* IOMMU / Intel VT-d / AMD-Vi
* PCIe protocol debugging
* Xilinx ILA / Intel SignalTap
* Hardware-security research

Please include information about previous FPGA/PCIe projects, FPGA families you have worked with, and the development toolchain you prefer.

I can provide the exact FPGA/DMA board model, FPGA chip, existing firmware information, reference hardware specifications, and test-environment details to the selected developer.