FPGA Firmware for PCIe Emulation

I’m looking for an experienced FPGA engineer to create a one-off firmware build for an Artix-7–based LeetDMA/Screamer PCIe DMA card. The goal is to make the card appear on the bus exactly like my reference network interface card so automated heuristic checks see no difference.

Scope of work
• Re-order and modify the Capability Pointer chain inside pcileech_pcie_cfg_a7.sv so the PCIe config space layout mirrors the donor NIC byte-for-byte.
• Implement full TLP transaction handling, including correct completion timing and status codes.
• Provide accurate BAR sizing and address decoding as the original NIC does.
• Add proper MSI / MSI-X interrupt setup with working vectors and masking logic.

Context and constraints
This firmware is for security research, not production deployment. Absolute fidelity to the donor network interface card is critical; any divergence in config space, BAR response, or interrupt behaviour will flag the device.

Deliverables
1. Complete Xilinx Vivado project (.xpr) with all updated .sv/.v source files.
2. Synthesizable, timing-clean design that meets default Artix-7 timing in Vivado.
3. Brief build README explaining how to regenerate the bitstream and where major edits were made.

Skills you’ll need: deep Verilog/SystemVerilog, PCIe protocol insight, Xilinx Vivado flow, and low-level hardware debugging. If you’ve previously spoofed or proxied PCIe devices, let me know—proof of similar work will stand out.

I’m ready to start as soon as I find the right match and will be available to test builds on hardware quickly.