Complete 5G Low-PHY FPGA Integration

I am developing a complete FPGA-based 5G NR Low-PHY platform for an O-RAN 7.2x radio architecture. The objective is to design, implement, integrate, optimize, and validate the complete real-time digital signal-processing chain rather than isolated FPGA blocks.

The scope covers O-RAN 7.2x/eCPRI fronthaul processing, IQ compression/decompression, FFT/IFFT and cyclic-prefix processing, resource and antenna mapping, 2×2 and 4×4 MIMO, precoding and digital beamforming, DUC/DDC, channelization, interpolation/decimation, digital filtering, CFR, DPD, calibration, gain/phase correction, multi-carrier processing, timing/synchronization, and high-speed ADC/DAC interfaces.

The engineer will be responsible for FPGA architecture, RTL/HLS/IP implementation, block integration, clock-domain and data-path design, fixed-point optimization, resource utilization, latency and throughput optimization, timing closure, simulation, hardware validation, debugging, and performance characterization!!

The platform should support configurable 5G NR bandwidths and numerologies, multiple carriers, 2×2 and 4×4 operation, and integration between the O-RAN fronthaul, Low-PHY/DFE processing, and RF/DAS hardware!

Preferred platform is AMD Xilinx Versal, with the final device selected according to processing, bandwidth, interface, and resource requirements.

The final objective is a modular, configurable, hardware-validated Low-PHY FPGA platform that can serve as the digital foundation for future 5G RU and DAS development!!!!!!!