Compile Cyclone FPGA Bitstream

I need a fresh Quartus build of the open-source USRP1 FPGA code at https://github.com/robincoxe/usrp1_openbts. I have added a roughly 100-line Verilog patch generated by AI for minor adjustments to improve performance. So, a compiled version has not been tested, but the unpatched version works well. The first step is simply getting the design through synthesis, place-and-route, and generating a working bitstream for the Cyclone target used by the USRP1 board.

No functional re-work or optimisation is required; I just want the patched design to compile cleanly with the standard settings already in the repository. You will therefore need a working installation of Intel/Altera Quartus (the version known to build this project is ideal) plus any supporting IP files the project expects.

Please return:

• The generated Cyclone .rbf bitstream
• The full Quartus build log or report showing a successful compile
• A zipped copy of the updated Quartus project directory so I can reproduce the build later

If the patch introduces errors, feel free to make the minimal code or constraint edits necessary to achieve a clean build, but keep changes clearly commented so I can review them.

Let me know your expected turnaround and which Quartus version you plan to use, and we can get started right away. I used Quartus 11 about a decade ago, but no longer have access to Quartus.