Analog Power Management Circuit Design

I’m an electrical and computer engineer with a concept in mind, but I’d like a fresh set of eyes to turn it into a rock-solid analog power-management circuit. The goal is a clean, efficient supply stage that can be dropped into a larger system without headaches.

Here’s what I need from you:
• A full schematic for the analog power-management section, sized for 12-24 V input and delivering stable, low-noise rails.
• Simulation files that verify efficiency, thermal behaviour, and worst-case tolerances. LTspice, PSpice, or Multisim are all fine—as long as I can rerun the results.
• A concise bill of materials with part numbers that are actually in stock at major distributors.
• If you’re comfortable, a first-pass PCB layout in KiCad or Altium would be a bonus, though not mandatory.

Acceptance criteria:
1. Simulated efficiency above 90 % at 1 A load.
2. Output ripple under 30 mV pp across 0 – 1 A.
3. All components rated for 105 °C or better.

I’m happy to discuss trade-offs, test points, or protection features such as OVP and soft start. Let me know how you’d tackle the design, which tools you prefer, and a realistic timeline for first deliverables.