AMD Ring-2 Firmware Development

I am putting together a small, focused engagement to extend System Management Mode into Ring -2 on modern AMD-based computers. The core of the job is writing low-level firmware/BIOS code that can initialise, enter, and reliably execute within this privileged context, exposing a clean interface that higher layers can later call.

What I already have:
• Reference boards on the latest AGESA release
• A minimal build environment based on UEFI/PI plus the usual toolchain (EDK II, GCC, OpenOCD for bare-metal debug)
• Test cases that confirm SMM entry under current firmware but do not yet drop into the Ring -2 enclave

What I need from you:
• Modify or replace the existing SMM handler so that it pivots into Ring -2 on AMD silicon without breaking ACPI or runtime services
• A concise interface document (function table, expected registers, error handling) so upper layers can call into the new code
• A simple proof-of-concept payload that shows code isolation and successful return to the OS

Acceptance criteria:
1. System posts and boots Windows or Linux unchanged.
2. SMIs still service all OEM functions (fan, power, etc.).
3. A bundled test utility reports successful Ring -2 execution and memory isolation in at least two different AMD chipsets I will supply.

You will have SSH access to a remote lab with serial-over-USB, JTAG, and logic analyser taps, and I am happy to schedule real-time sessions if you need hardware eyes on the board.

the target is a cheat that remains untraced by kernel-level and hypervisor-level anti-cheat, not merely a functional SMM module

Acknowledgment of the AMD USB-SMI limitation, with a plan for how you intend to resolve it (chipset-specific SMI routing, a different input path, or accepting that the USB requirement may not be satisfiable on your boards)

Acceptance criteria that include detection-resistance testing, such as SMI counter visibility, PMC anomalies, and SMRAM access patterns—not just "it boots" and "a test utility says yes."

A realistic hardware matrix: Plouton's Intel support spans Series 200 through Series 700 with Series 800 untested; the AMD memory-core reuse is plausible, but the USB path is the open question

If low-level silicon work, AGESA dives, and SMM quirks are your comfort zone, let’s talk.