4-Layer ESP32 Hardware Optimization & Thermal Simulation (Current: 85% Schematic)

4-Layer ESP32 Hardware Optimization & Thermal Simulation (Current: 85% Schematic)

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PROJECT BUDGET & BIDDING TERMS:
• Budget: Strict Fixed Price between $40.00 USD and $70.00 USD.
• Selection Criteria: The best, most technically sound proposal strictly within this budget range ($40 - $70) will be awarded immediately.
• NDA Required: A signed NDA is mandatory prior to releasing existing KiCad schematic source files.
• Notice: Bids exceeding $70 or generic placeholder bids will be ignored automatically.
• Anti-Spam Check: Start your proposal with the exact passphrase: "TITAN-VALIDATED".
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### Project Overview:
We are seeking a Senior Hardware / Embedded Electronics Engineer to perform an end-to-end design audit, simulation, schematic completion, 4-layer PCB layout, and thermal/reliability validation for an industrial-grade ESP32 controller board. Schematic is currently ~85% complete in KiCad.

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### Appendix A: Scope of Work and Deliverables

#### Milestone 1: Schematic Audit, Peripheral Integration & Electrical Simulation

##### A. Scope of Work (Milestone 1)
1. **Circuit Simulation & Power Integrity (PI/PDN):**
- Full audit of current KiCad schematic; fix industrial design flaws.
- Simulate and validate critical sub-circuits, transient behavior, and PDN stability in Siemens HyperLynx / LTspice before routing.
- PDN/PI analysis: Optimize plane impedance, decoupling capacitor selection/placement, voltage stability, and noise suppression across all rails.
- Startup and transient load noise analysis.

2. **Schematic Review & Hardware Integration:**
- **BOM Optimization:** Replace high-cost, long lead-time, single-source, or NRND/EOL parts with active, reliable, dual-sourced alternatives (DigiKey/Mouser/LCSC) without compromising performance.
- **MCU & Module Interfacing:**
- Route 2 spare HLK GPIOs to ESP32 EN & GPIO0; connect HLK UART to ESP32 UART0 (shared GND) for boot mode control/reflashing via HLK (verify pull-ups/debounce prevent accidental bootloader entry on HLK reboot).
- Route HLK USB lines to add a MicroSD card slot.
- Add 1x PoE RJ45 connector & 12V output DC barrel jack.
- Add 1x RS485 connector using THVD1400D transceiver.
- Add ES7210 (4-ch differential ADC) for 2x differential analog MIC inputs.
- Add 2x MAX98357A (mono I2S Class-D amps on shared I2S bus, split via SD_MODE) for 2x Class-D BTL speaker outputs (verify zero pin conflicts with strapping, flash, or RS485).
- **Added I/O & Connectors:**
- 1x Illuminated ON/OFF Switch Connector (JST): Low-side N-Channel MOSFET for LED, hardware RC debounce (10kΩ pull-up + 100nF cap), TVS ESD clamping diode.
- 4x Dry-Contact Sensor Connectors (2-Pin JST): Hardware RC debounce (10kΩ + 100nF) + bidirectional TVS ESD diodes on each.
- 2x Active Sensor Connectors (3-Pin JST: VCC, GND, SIG): Resettable PTC Polyfuse on VCC, 100nF decoupling, TVS ESD diode on signal.
- **COTS Peripherals Specification (Dedicated BOM Section):**
- Select and specify manufacturer MPNs, datasheets, sourcing links, and mating pre-crimped JST harnesses for:
(1) 2x IP65/IP67 enclosed cavity speakers (8Ω 2W)
(2) 2x IP67 waterproof analog ECM mic capsules (silicone boots + hydrophobic membrane)
(3) 1x IP65/IP67 illuminated metal momentary/latching pushbutton (O-ring sealed)
(4) 4x IP67 waterproof door reed switches
(5) 2x outdoor weather-sealed active motion sensors (PIR / 24GHz mmWave radar 0-1m).
- **Hardware Design Constraints:**
- Polarized/keyed connectors (JST-XH 2.54mm or JST-PH 2.0mm) with clear Pin 1 silk screen.
- TVS diodes placed immediately adjacent to connector pins ahead of MCU tracks.
- **Power Architecture & Sequencing:**
- 12V, 5V, and 3.3V rails must fully stabilize before ESP32 EN/Reset is pulled high (brownout prevention).
- TPS e-fuse & buck stages: Soft-start and inrush current limiting under high capacitive loads.
- Connect TPS PG pin to buck converter EN pins and to ESP32 GPIO.
- Verify resistor divider on TPS EN line (UVLO protection, max 7V rating).
- Connect TPS LDSTRT to ESP32 GPIO via timer logic for startup handshake.
- Connect PG pin of each buck converter to separate ESP32 GPIOs; TPS IMON to ADC-capable GPIO.
3. **Safety & Isolation:**
- Establish galvanic isolation strategy, defining creepage and clearance rules between high-power AC/DC tracks and low-voltage logic/RF sections.

##### B. Milestone 1 Deliverables
- Fully organized, unencrypted KiCad schematic source files and custom project libraries (symbols/footprints).
- Preliminary Production BOM & External COTS Build BOM (Excel/CSV with MPNs, lifecycle status, sourcing links).
- ERC Report (zero critical violations).
- Native simulation files (.hyp, .asc, or LTspice profile files) and exported waveform/impedance reports.
- Preliminary Isolation & Safety Design Note (creepage/clearance).

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#### Milestone 2: 4-Layer PCB Layout, Thermal/Reliability Simulation & Production Package

##### A. Scope of Work (Milestone 2)
1. **PCB Design & Layout (4-Layer):**
- Industrial DFM/DFA compliant layout.
- Dedicated AGND and DGND separation for ES7210 and MAX98357A, tied at a single star-ground point to eliminate audio hum and switching noise.
- Strict galvanic isolation and clearance between high-power tracks and low-voltage logic/RF.
- Full compliance with Espressif hardware design guidelines for ESP32 module placement and RF keepout.
2. **Thermal & Reliability Simulation:**
- Full FEA/CFD Thermal Simulation (ANSYS Icepak or Siemens Simcenter Flotherm) under continuous 24/7 load across -10°C to +65°C ambient.
- Reliability assessment for up to 95% RH humidity and component derating (capacitors ≥105°C, voltage derated by 20-30%) proving 5+ years operational lifetime (Arrhenius / IPC-9592 standards).
- Identify hotspots (HLK module, power stages) and apply mitigations (thermal vias, copper pours).
3. **Testing, Programming & Manufacturing Prep:**
- Dedicated ICT test points for 3.3V, 12V, GND, and critical signals.
- Flashing interface with auto-reset circuit for ESP32.
- DFM/DFA checks and panelization support.
- Post-manufacturing bring-up support for design-related flaws.

##### B. Milestone 2 Deliverables
- Native KiCad PCB layout and schematic files.
- PCB Stackup Definition (layer count, copper weight, dielectric specs).
- HyperLynx DRC / EMI DRC Report (zero critical errors).
- Thermal Simulation Package: Native source files (ANSYS Icepak / Flotherm), high-res simulation video demo, and detailed PDF report with 3D thermal heat maps.
- Reliability Package: Component Derating & 5-Year Lifetime Estimation Report.
- 3D STEP Assembly Model (.step).
- Manufacturing Package: Gerbers (RS-274X/X2), NC Drill, ODB++ or IPC-2581, IPC-D-356 Netlist, Final Verified Netlist, Centroid (Pick & Place), Assembly Drawings (PDF), Fabrication Notes & Specs Sheet (ENIG, copper weights, IPC class).
- Solder Paste (Stencil) Files (Top/Bottom).
- Production BOM (including 2x KH-FPC2.4G-1.13IPEX-240 Antennas & secondary alternates).
- Manufacturing Readiness Reports (DFM/DFA) & Signed Manufacturing Release Checklist.
- Test Strategy & Bring-up Package: Test points map, power-up checklist, flashing guide, and Hardware-to-Software GPIO Mapping Sheet.
- Panelization Support: Panelized Gerber layout with fiducials and break-away tabs.
- Technical Documentation: Creepage/Clearance Isolation Note, Design Revision Log, Controlled Impedance & SI Report (HyperLynx SI / Z-Planner: 90Ω USB, 100Ω RS485/HUB75, 50Ω RF), and Engineering Calculation Package.

Note: We require an NDA